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7.2.14 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO 0 and IO 1 . It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to
input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7 -0) after the input Address bits (A23-0), as shown in Figure 13a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3- 0) are don’t care
(“x”). However, the IO pins should be high -impedance prior to the falling edge of the first data out clock.
If t he “Continuous Read Mode ” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS
is raised and then lowered) does not require the BBh instruction code, as shown in Figure 13b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered
after /CS is asserted low. If the “Continuous Read Mode ” bits M5-4 do not equal to (1,0), the next
instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to
normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset (M7 -0) before
issuing normal instructions (See 7.2.20 for detail descriptions).
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
Mode 0
Instruction (BBh)
A23-16
A15-8
A7-0
M7-0
DI
(IO 0 )
22
20
18
16
14
12
10
8
6
4
2
0
6
4
2
0
DO
(IO 1 )
* = MSB
23
*
21
19
17
15
13
11
9
7
5
3
1
7
*
5
3
1
/CS
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
CLK
IOs switch from
Input to Output
DI
(IO 0 )
DO
(IO 1 )
0
1
6
7
*
4
5
2
3
Byte 1
0
1
6
7
*
4
5
2
3
Byte 2
0
1
6
7
*
4
5
2
3
Byte 3
0
1
6
7
*
4
5
2
3
Byte 4
0
1
6
7
Figure 13a. Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4 ? 10)
Publication Release Date: October 03, 2013
- 31 -
Revision G
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